A new single Miller capacitor for frequency compensation of three-stage amplifier is proposed in this paper. In this scheme, a differential stage in which its negative and positive inputs are connected to the output and input nodes of third stage with a cascade capacitor forms the compensation block of a conventional three-stage amplifier. Analysis shows that this configuration significantly improves the frequency domain performances of total circuit such as phase margin (PM) and gain-bandwidth product (GBW) with just a very small amount of compensation capacitor. A three-stage amplifier has been simulated with and without a differential feedback path in a 0.18 µm complementary metal–oxide–semiconductor (CMOS). The simulated amplifier with a 100 pF capacitive load achieved more than 9 MHz GBW and 83° PM while the compensation is less than 0.2% of load capacitor. An amplifier based on conventional nested Miller compensation can just achieve less than 0.23 MHz GBW with the same load, while using more than 100 pF as compensation capacitor. So this method shows an improvement of a factor of 40 in GBW and reduction of a factor of 550 in the size of compensation capacitor. It is a suitable strategy for ON-CHIP compensation in comparison to other methods